1. Field of the Invention
The present invention relates to a method of forming a copper wiring in a semiconductor device and, more specifically, to a method of forming a copper wiring in a semiconductor device capable of improving reliability of the wiring by increasing an interfacial bondability of a copper anti-diffusion insulating film with each of a copper wiring and an insulating film underlying the insulating film.
2. Discussion of Related Art
Generally, as the semiconductor industry shifts to an ultra large-scale integration (ULSI) level, the geometry of the device continues to be narrowed to a sub-half-micron region. In view of improved performance and reliability, the circuit density is gradually increased. Copper has a high resistance to electro-migration (EM) since it has a higher melting point than aluminum. Thus copper can improve reliability of the device. Further, copper can increase a signal transfer speed since it has a low resistivity. For this reason, in forming a metal wiring in a semiconductor device, copper has been used as an interconnection material useful for an integration circuit.
A method of burying copper that may be used currently includes a physical vapor deposition (PVD) method/reflow method, a chemical vapor deposition (CVD) method, an electroplating method, an electroless-plating method and the like. Preferred methods of them are the electroplating method and the CVD method, which have a relatively good copper burial characteristic.
While copper is used as the material of the metal wiring, a damascene scheme for simultaneously forming a via contact hole for electrical connection to a lower layer and a trench in which the metal wiring is located, has been widely used along with the process of forming the copper wiring in the semiconductor device. A low-dielectric insulating material having a low dielectric constant is used as the interlayer insulating film in which the damascene pattern will be formed.
In order to form the copper wiring in the damascene pattern having the via contact hole and the trench, copper is buried into the damascene pattern through several methods and the buried copper layer is then polished by a CMP process, thus making the buried copper layer isolated from neighboring copper wirings.
FIG. 1 is a sectional view for explaining the method of forming the copper wiring in the semiconductor device according to a prior art.
A first interlayer insulating film 12 and an anti-polishing layer 13 are formed on a substrate 11. The anti-polishing layer 13 and the first interlayer insulating film 12 are etched by a damascene scheme to form a damascene pattern 14.
A copper anti-diffusion conductive film 15 is formed along the surface of the anti-polishing layer 13 including the damascene pattern 14. A copper layer is then formed enough to sufficiently bury the damascene pattern 14. Next, the CMP process is performed until the anti-polishing layer 13 is exposed, thus forming a copper wiring 16 within the damascene pattern 14. Thereafter, a copper anti-diffusion insulating film 17 and a second interlayer insulating film 18 are formed on the entire structure including the copper wiring 16.
In the above-mentioned method, in order to prevent diffusion of copper elements from the copper wiring 16 to the outside, the copper wiring 16 is sealed using the copper anti-diffusion conductive film 15 and the copper anti-diffusion insulating film 17. In the device having the copper wiring 16 formed by the conventional method, however, most defective wiring generated by electro-migration and stress migration occurs at the interface between the copper anti-diffusion insulating film 17 and the copper anti-diffusion conductive film 15, as indicated by an arrow “A”. This condition is caused by a lack in the interfacial bondability of the copper anti-diffusion insulating film 17 and the lower layers 13, 15 and 16.